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92
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EICS
2010
ACM
14 years 10 months ago
An automated routine for menu structure optimization
We propose an automated routine for hierarchical menu structure optimization. A computer advice-giving system founded on the mathematical model of menu navigation directs the desi...
Mikhail V. Goubko, Alexander I. Danilenko
ISCAS
1999
IEEE
146views Hardware» more  ISCAS 1999»
15 years 4 months ago
Optimization of CMOS MEMS microwave power sensors
- Micromachined power sensors with operation up to 50 GHz were recently achieved in CMOS technology [1]. To improve their sensitivity and signal-to-noise ratio, while maintaining m...
V. Milanovic, M. Hopcroft, C. A. Zincke, M. Gaitan...
106
Voted
FPGA
2003
ACM
120views FPGA» more  FPGA 2003»
15 years 5 months ago
Architecture evaluation for power-efficient FPGAs
This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contri...
Fei Li, Deming Chen, Lei He, Jason Cong
ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
15 years 9 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
109
Voted
VLSID
2002
IEEE
151views VLSI» more  VLSID 2002»
16 years 29 days ago
Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems
Among the many techniques for system-level power management, it is not currently possible to guarantee timing constraints and have a comprehensive system model at the same time. S...
Dexin Li, Pai H. Chou, Nader Bagherzadeh