731 search results - page 72 / 147 » Interconnect modeling for improved system-level design optim... |
ISCAS
2006
IEEE
15 years 6 months ago
2006
IEEE
The efficient design of multiplierless implementa- The goal is to find the optimal sub-expressions across all N dot tions of constant matrix multipliers is challenged by the huge p...
102
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CCGRID
2003
IEEE
15 years 5 months ago
2003
IEEE
— Due to enormous complexity of the unstructured peer-to-peer networks as large-scale, self-configure, and dynamic systems, the models used to characterize these systems are eit...
108
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HPCA
2009
IEEE
16 years 1 months ago
2009
IEEE
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
112
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ASPDAC
2006
ACM
15 years 6 months ago
2006
ACM
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
126
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ICC
2009
IEEE
14 years 10 months ago
2009
IEEE
Abstract-- Wireless sensor networks (WSNs) require energyef cient protocols to improve the network lifetime. In this work, we adopt a cross-layer strategy that considers routing an...