34 search results - page 5 / 7 » Interconnect power and delay optimization by dynamic program... |
MICRO
2009
IEEE
14 years 1 months ago
2009
IEEE
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
ICCAD
1997
IEEE
13 years 10 months ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
ISPD
2009
ACM
14 years 1 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
ISPD
2012
ACM
12 years 2 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
MICRO
2003
IEEE
13 years 11 months ago
2003
IEEE
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...