21 search results - page 3 / 5 » Interconnect scaling implications for CAD |
126
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TVLSI
2008
15 years 1 months ago
2008
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...
DATE
2005
IEEE
15 years 7 months ago
2005
IEEE
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...
123
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SAINT
2005
IEEE
15 years 7 months ago
2005
IEEE
In this paper, we propose an analytic approach of modeling a closed-loop network with multiple feedback loops using fluid-flow approximation. Specifically, we model building bl...
ICCAD
2001
IEEE
15 years 10 months ago
2001
IEEE
In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. T...
118
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EUROPAR
2009
Springer
15 years 8 months ago
2009
Springer
The size of supercomputers in numbers of processors is growing exponentially. Today’s largest supercomputers have upwards of a hundred thousand processors and tomorrow’s may ha...