60 search results - page 9 / 12 » Interface Design for Rationally Clocked GALS Systems |
105
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TCAD
2008
14 years 11 months ago
2008
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while follo...
CODES
2006
IEEE
15 years 5 months ago
2006
IEEE
The ability to do fine grain power management via local voltage selection has shown much promise via the use of Voltage/ Frequency Islands (VFIs). VFI-based designs combine the a...
EXPCS
2007
15 years 3 months ago
2007
Experimental computer systems research typically ignores the end-user, modeling him, if at all, in overly simple ways. We argue that this (1) results in inadequate performance eva...
122
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PPL
2008
14 years 11 months ago
2008
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
113
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BMCBI
2007
14 years 11 months ago
2007
Background: RNA interference has revolutionized our ability to study the effects of altering the expression of single genes in mammalian (and other) cells through targeted knockdo...