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2003
IEEE
112views Hardware» more  DATE 2003»
15 years 5 months ago
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0
The concept of a SOC platform architecture introduces the concept of a communication infrastructure. In the transaction-level a finite set of architecture components (memories, ar...
Marco Caldari, Massimo Conti, Massimo Coppola, Ste...
DAC
2003
ACM
16 years 24 days ago
Instruction encoding synthesis for architecture exploration using hierarchical processor models
This paper presents a novel instruction encoding generation technique for use in architecture exploration for application specific processors. The underlying exploration methodolo...
Achim Nohl, Volker Greive, Gunnar Braun, Andreas H...
MOMPES
2008
IEEE
15 years 6 months ago
Architectural Concurrency Equivalence with Chaotic Models
During its lifetime, embedded systems go through multiple changes to their runtime architecture. That is, threads, processes, and processor are added or removed to/from the softwa...
Dionisio de Niz
IEEEAMS
2002
IEEE
15 years 4 months ago
Understanding Consistency Maintenance in Service Discovery Architectures in Response to Message Loss
Current trends suggest future software systems will comprise collections of components that combine and recombine dynamically in reaction to changing conditions. Service-discovery...
Christopher Dabrowski, Kevin L. Mills, Jesse Elder
INFOCOM
2000
IEEE
15 years 4 months ago
Fast and Scalable Priority Queue Architecture for High-Speed Network Switches
-In this paper, we present a fast and scalable pipelined priority queue architecture for use in high-performance switches with support for fine-grained quality of service (QoS) gu...
Ranjita Bhagwan, Bill Lin