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ATAL
2006
Springer
15 years 3 months ago
Designing agent chips
We outline meta-encoding schemas for compiling nonmonotonic logic theories into Verilog HDL (Hardware Description Language) descriptions. These descriptions can be synthesized int...
Insu Song, Guido Governatori
SC
2009
ACM
15 years 6 months ago
Enabling high-fidelity neutron transport simulations on petascale architectures
The UNIC code is being developed as part of the DOE’s Nuclear Energy Advanced Modeling and Simulation (NEAMS) program. UNIC is an unstructured, deterministic neutron transport c...
Dinesh K. Kaushik, Micheal Smith, Allan Wollaber, ...
VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
16 years 7 days ago
Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
M. S. Gaur, Mark Zwolinski
PADL
2007
Springer
15 years 6 months ago
BAD, a Declarative Logic-Based Language for Brain Modeling
Abstract. We describe a declarative language, called BAD (brain architecture description language), which we have developed for describing and then running brain models. Models are...
Alan H. Bond
DELTA
2010
IEEE
15 years 5 months ago
Notations for Multiphase Pipelines
— FPGAs, (Field-Programmable Gate Arrays) are often used for embedded image processing applications. Parallelism, and in particular pipelining, is the most suitable architecture ...
Christopher T. Johnston, Donald G. Bailey, Paul J....