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MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
14 years 9 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim
HIPC
2003
Springer
15 years 4 months ago
Designing SANs to Support Low-Fanout Multicasts
Abstract. System area networks (SANs) need to support low-fanout multicasts efficiently in addition to broadcasts and unicasts. A critical component in SANs is the switch, which i...
Rajendra V. Boppana, Rajesh Boppana, Suresh Chalas...
SIGCOMM
1995
ACM
15 years 2 months ago
Pipelined Memory Shared Buffer for VLSI Switches
ABSTRACT: Switch chips are building blocks for computer and communication systems. Switches need internal buffering, because of output contention; shared buffering is known to perf...
Manolis Katevenis, Panagiota Vatsolaki, Aristides ...
MICRO
2003
IEEE
99views Hardware» more  MICRO 2003»
15 years 4 months ago
Power-driven Design of Router Microarchitectures in On-chip Networks
As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors, networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric for on-...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
WCE
2007
15 years 17 days ago
Dynamic Scheduling Algorithm for input-queued crossbar switches
— Crossbars are main components of communication switches used to construct interconnection networks. Scheduling algorithm controls contention in switch architecture. Several sch...
Mihir V. Shah, Mehul C. Patel, Dinesh J. Sharma, A...