40 search results - page 4 / 8 » Internet-Router Buffered Crossbars Based on Networks on Chip |
SIGCOMM
2004
ACM
15 years 2 months ago
2004
ACM
−Buffered multistage interconnection networks offer one of the most scalable and cost-effective approaches to building high capacity routers. Unfortunately, the performance of su...
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CICC
2011
13 years 9 months ago
2011
Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of...
ICC
2007
IEEE
15 years 3 months ago
2007
IEEE
1 Routers need buffers to store and forward packets, especially when there is network congestion. With current memory technology, neither the SRAM nor the DRAM alone is suitabl...
HPCA
1996
IEEE
15 years 1 months ago
1996
IEEE
The current multiprocessors such asCray T3D support interprocessor communication using partitioned dimension-order routers (PDRs). In a PDR implementation, the routing logic and sw...
AHS
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents a new approach in realizing Virtual Channels tailored for Network on Chip implementations. The technique makes use of a flow control mechanism based on adaptiv...