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VLSID
2009
IEEE
99views VLSI» more  VLSID 2009»
16 years 5 days ago
Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips
In this paper, we present a dynamic power management technique for optimizing the use of virtual channels in network on chips. The technique which is called dynamic virtual channe...
Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afz...
HPCA
2003
IEEE
15 years 12 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
MICRO
2006
IEEE
98views Hardware» more  MICRO 2006»
15 years 5 months ago
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring...
Chrysostomos Nicopoulos, Dongkook Park, Jongman Ki...
VLSID
2004
IEEE
292views VLSI» more  VLSID 2004»
15 years 12 months ago
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
Jeremy Chan, Sri Parameswaran
ISCA
2009
IEEE
214views Hardware» more  ISCA 2009»
15 years 6 months ago
Phastlane: a rapid transit optical routing network
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable c...
Mark J. Cianchetti, Joseph C. Kerekes, David H. Al...