40 search results - page 6 / 8 » Internet-Router Buffered Crossbars Based on Networks on Chip |
GLVLSI
2005
IEEE
15 years 3 months ago
2005
IEEE
We have presented an optimal on-chip buffer allocation and buffer insertion methodology which uses stochastic models of the architecture. This methodology uses finite buffer s...
CODES
2008
IEEE
14 years 11 months ago
2008
IEEE
The performance of system-on-chip is determined not only by the performance of its functional units, but also by how efficiently they cooperate with one another. It is the on-chip...
ASYNC
2005
IEEE
15 years 3 months ago
2005
IEEE
Networks on Chip that can guarantee Quality of Service (QNoC) are based on special routers that can support multiple service levels. GALS SoCs call for asynchronous NoC implementa...
QEST
2007
IEEE
15 years 3 months ago
2007
IEEE
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri...
DAC
2007
ACM
15 years 10 months ago
2007
ACM
We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To s...