928 search results - page 33 / 186 » Interpolation-sequence based model checking |
QEST
2008
IEEE
15 years 4 months ago
2008
IEEE
CaVi provides a uniform interface to state-of-the-art simulation methods and formal verification methods for wireless sensor network. Simulation is suitable to examine the behavi...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
ASM
2008
ASM
14 years 12 months ago
2008
ASM
As systems become ever more complex, verification becomes more main stream. Event-B and Alloy are two formal specification languages based on fairly different methodologies. While...
103
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ENTCS
2006
14 years 10 months ago
2006
Bounded Model Checking (BMC) searches for counterexamples to a property with a bounded length k. If no such counterexample is found, k is increased. This process terminates when ...
170
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POPL
2005
ACM
15 years 10 months ago
2005
ACM
We present a new approach to partial-order reduction for model checking software. This approach is based on initially exploring an arbitrary interleaving of the various concurrent...