Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
Separation logic is a subset of the quantifier-free first order logic. It has been successfully used in the automated verification of systems that have large (or unbounded) inte...
Chao Wang, Franjo Ivancic, Malay K. Ganai, Aarti G...
Abstract. In this paper we report a new SAT solver for difference logic, a propositional logic enriched with timing constraints. The main novelty of our solver is a tighter integra...
Scott Cotton, Eugene Asarin, Oded Maler, Peter Nie...
Craig interpolation is a well known method of abstraction successfully used in both hardware and software model checking. The logical strength of interpolants can affect the quali...
Simone Fulvio Rollini, Ondrej Sery, Natasha Sharyg...
This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...