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» Interpolative Boolean Logic
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TCAD
2008
112views more  TCAD 2008»
14 years 9 months ago
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
LPAR
2005
Springer
15 years 2 months ago
Deciding Separation Logic Formulae by SAT and Incremental Negative Cycle Elimination
Separation logic is a subset of the quantifier-free first order logic. It has been successfully used in the automated verification of systems that have large (or unbounded) inte...
Chao Wang, Franjo Ivancic, Malay K. Ganai, Aarti G...
FORMATS
2004
Springer
15 years 1 months ago
Some Progress in Satisfiability Checking for Difference Logic
Abstract. In this paper we report a new SAT solver for difference logic, a propositional logic enriched with timing constraints. The main novelty of our solver is a tighter integra...
Scott Cotton, Eugene Asarin, Oded Maler, Peter Nie...
CAV
2012
Springer
222views Hardware» more  CAV 2012»
12 years 12 months ago
Leveraging Interpolant Strength in Model Checking
Craig interpolation is a well known method of abstraction successfully used in both hardware and software model checking. The logical strength of interpolants can affect the quali...
Simone Fulvio Rollini, Ondrej Sery, Natasha Sharyg...
FPL
2005
Springer
96views Hardware» more  FPL 2005»
15 years 3 months ago
FPGA PLB Evaluation using Quantified Boolean Satisfiability
This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...