Design and verification of systems at the Register-Transfer (RT) or behavioral level require the ability to reason at higher levels of abstraction. Difference logic consists of an...
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Using a new exact synthesizer that automatically induces minimal universal boolean function libraries, we introduce two indicators for comparing their expressiveness: the first ba...
SAT-based decision procedures for quantifier-free fragments of firstorder logic have proved to be useful in formal verification. These decision procedures are either based on enco...
Sanjit A. Seshia, Shuvendu K. Lahiri, Randal E. Br...
The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of...
Victor Khomenko, Maciej Koutny, Alexandre Yakovlev