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» Interpolative Boolean Logic
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FORMATS
2006
Springer
15 years 4 months ago
Temporal Logic Verification Using Simulation
In this paper, we consider a novel approach to the temporal logic verification problem of continuous dynamical systems. Our methodology has the distinctive feature that enables the...
Georgios E. Fainekos, Antoine Girard, George J. Pa...
ITC
1995
IEEE
122views Hardware» more  ITC 1995»
15 years 4 months ago
A Fault Model and a Test Method for Analog Fuzzy Logic Circuits
A nalog circuit implementations of fuzzy logic are characterized by performing logical connectives of analog signals. They can be considered as generalization of digital circuits ...
Stefan Weiner
122
Voted
FOCS
1998
IEEE
15 years 5 months ago
The Complexity of Acyclic Conjunctive Queries
This paper deals with the evaluation of acyclic Boolean conjunctive queries in relational databases. By well-known results of Yannakakis [1981], this problem is solvable in polynom...
Georg Gottlob, Nicola Leone, Francesco Scarcello
115
Voted
CHARME
2003
Springer
196views Hardware» more  CHARME 2003»
15 years 6 months ago
Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT
We present a non-operational approach to specifying and analyzing shared memory consistency models. The method uses higher order logic to capture a complete set of ordering constra...
Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom, K...
FPGA
2001
ACM
145views FPGA» more  FPGA 2001»
15 years 5 months ago
Simultaneous logic decomposition with technology mapping in FPGA designs
Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
Gang Chen, Jason Cong