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TACAS
2004
Springer
108views Algorithms» more  TACAS 2004»
15 years 2 months ago
Model Checking Discounted Temporal Properties
Temporal logic is two-valued: formulas are interpreted as either true or false. When applied to the analysis of stochastic systems, or systems with imprecise formal models, tempor...
Luca de Alfaro, Marco Faella, Thomas A. Henzinger,...
ICCAD
1999
IEEE
148views Hardware» more  ICCAD 1999»
15 years 1 months ago
SAT based ATPG using fast justification and propagation in the implication graph
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...
Paul Tafertshofer, Andreas Ganz
DAC
2003
ACM
15 years 10 months ago
A new enhanced constructive decomposition and mapping algorithm
Structuring and mapping of a Boolean function is an important problem in the design of complex integrated circuits. Libraryaware constructive decomposition offers a solution to th...
Alan Mishchenko, Xinning Wang, Timothy Kam
ICCAD
2006
IEEE
128views Hardware» more  ICCAD 2006»
15 years 6 months ago
Improvements to combinational equivalence checking
The paper explores several ways to improve the speed and capacity of combinational equivalence checking based on Boolean satisfiability (SAT). State-of-the-art methods use simulat...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
ATVA
2007
Springer
162views Hardware» more  ATVA 2007»
15 years 3 months ago
Verifying Heap-Manipulating Programs in an SMT Framework
Automated software verification has made great progress recently, and a key enabler of this progress has been the advances in efficient, automated decision procedures suitable fo...
Zvonimir Rakamaric, Roberto Bruttomesso, Alan J. H...