63 search results - page 11 / 13 » Interprocedural Load Elimination for Dynamic Optimization of... |
MICRO
2000
IEEE
15 years 2 months ago
2000
IEEE
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...
SC
2005
ACM
15 years 3 months ago
2005
ACM
The memory consistency model in parallel programming controls the order in which operations performed by one thread may be observed by another. Language designers have been reluct...
ICS
2007
Tsinghua U.
15 years 4 months ago
2007
Tsinghua U.
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
PLDI
1998
ACM
15 years 2 months ago
1998
ACM
This paper evaluates three alias analyses based on programming language types. The first analysis uses type compatibility to determine aliases. The second extends the first by u...
LCTRTS
2007
Springer
15 years 4 months ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...