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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
15 years 8 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
121
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ATAL
2003
Springer
15 years 4 months ago
Authoring scenes for adaptive, interactive performances
In this paper, we introduce a toolkit called SceneMaker for authoring scenes for adaptive, interactive performances. These performances are based on automatically generated and pr...
Patrick Gebhard, Michael Kipp, Martin Klesen, Thom...
SIGARCH
2008
73views more  SIGARCH 2008»
14 years 11 months ago
Servo: a programming model for many-core computing
Conventional programming models were designed to be used by expert programmers for programming for largescale multiprocessors, distributed computational clusters, or specialized p...
Nicolas Zea, John Sartori, Rakesh Kumar
CVPR
2007
IEEE
16 years 1 months ago
OpenVL: Towards A Novel Software Architecture for Computer Vision
This paper presents our progress on OpenVL - a novel software architecture to address efficiency through facilitating hardware acceleration, reusability and scalability for comput...
Changsong Shen, S. Sidney Fels, James J. Little
NOSSDAV
2010
Springer
15 years 4 months ago
RTP-miner: a real-time security framework for RTP fuzzing attacks
Real-time Transport Protocol (RTP) is a widely adopted standard for transmission of multimedia traffic in Internet telephony (commonly known as VoIP). Therefore, it is a hot poten...
M. Ali Akbar, Muddassar Farooq