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GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
12 years 10 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...
ICPP
1998
IEEE
13 years 10 months ago
Concurrent SSA Form in the Presence of Mutual Exclusion
Most current compiler analysis techniques are unable to cope with the semantics introduced by explicit parallel and synchronization constructs in parallel programs. In this paper ...
Diego Novillo, Ronald C. Unrau, Jonathan Schaeffer
SPAA
2005
ACM
13 years 12 months ago
Concurrent cache-oblivious b-trees
This paper presents concurrent cache-oblivious (CO) B-trees. We extend the cache-oblivious model to a parallel or distributed setting and present three concurrent CO B-trees. Our ...
Michael A. Bender, Jeremy T. Fineman, Seth Gilbert...
ERSHOV
2006
Springer
13 years 10 months ago
Streaming Networks for Coordinating Data-Parallel Programs
A new coordination language for distributed data-parallel programs is presented, call SNet. The intention of SNet is to introduce advanced structuring techniques into a coordinatio...
Clemens Grelck, Sven-Bodo Scholz, Alexander V. Sha...
NCA
2007
IEEE
14 years 19 days ago
Improving Network Processing Concurrency using TCPServers
Exponentially growing bandwidth requirements and slowing gains in processor speeds have led to the popularity of multiprocessor architectures. Network stack parallelism is increas...
Aniruddha Bohra, Liviu Iftode