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IEEEPACT
2009
IEEE
14 years 11 months ago
Cache Sharing Management for Performance Fairness in Chip Multiprocessors
Resource sharing can cause unfair and unpredictable performance of concurrently executing applications in Chip-Multiprocessors (CMP). The shared last-level cache is one of the mos...
Xing Zhou, Wenguang Chen, Weimin Zheng
ESOP
1998
Springer
15 years 5 months ago
Mode-Automata: About Modes and States for Reactive Systems
Abstract. In the eld of reactive system programming, data ow synchronous languages like Lustre BCH+85,CHPP87 or Signal GBBG85 o er a syntax similar to block-diagrams, and can be e ...
Florence Maraninchi, Yann Rémond
CODES
2005
IEEE
15 years 7 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
IPPS
2006
IEEE
15 years 7 months ago
Exploiting processing locality through paging configurations in multitasked reconfigurable systems
FPGA chips in reconfigurable computer systems are used as malleable coprocessors where components of a hardware library of functions can be configured as needed. As the number of ...
T. Taher, Tarek A. El-Ghazawi
STACS
1995
Springer
15 years 4 months ago
Generalized Scans and Tri-Diagonal Systems
Motivatedby the analysis of known parallel techniques for the solution of linear tridiagonal system, we introduce generalized scans, a class of recursively de ned lengthpreserving...
Paul F. Fischer, Franco P. Preparata, John E. Sava...