The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging pr...
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
—The design of optimal opportunistic multicast scheduling (OMS) that maximizes the throughput of cellular networks is investigated. In a cellular network, the base station (BS) t...
Abstract— Achieving minimal loss while satisfying an acceptable delay profile remains to be an open problem under the RED queuing discipline. In this paper, we present a framewo...
Homayoun Yousefi'zadeh, Amir Habibi, Hamid Jafarkh...