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DAC
2007
ACM
16 years 5 months ago
SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty
ISQED
2010
IEEE
177views Hardware» more  ISQED 2010»
15 years 11 months ago
Multi-corner, energy-delay optimized, NBTI-aware flip-flop design
With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging pr...
Hamed Abrishami, Safar Hatami, Massoud Pedram
ASAP
2008
IEEE
142views Hardware» more  ASAP 2008»
15 years 11 months ago
Managing multi-core soft-error reliability through utility-driven cross domain optimization
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
Wangyuan Zhang, Tao Li
GLOBECOM
2008
IEEE
15 years 11 months ago
Optimized Opportunistic Multicast Scheduling over Cellular Networks
—The design of optimal opportunistic multicast scheduling (OMS) that maximizes the throughput of cellular networks is investigated. In a cellular network, the base station (BS) t...
Tze-Ping Low, Man-On Pun, C. C. Jay Kuo
ICC
2008
IEEE
114views Communications» more  ICC 2008»
15 years 11 months ago
Optimal Statistical Tuning of the RED Parameters
Abstract— Achieving minimal loss while satisfying an acceptable delay profile remains to be an open problem under the RED queuing discipline. In this paper, we present a framewo...
Homayoun Yousefi'zadeh, Amir Habibi, Hamid Jafarkh...