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93
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DAC
2007
ACM
16 years 1 months ago
SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty
CCR
2004
116views more  CCR 2004»
15 years 7 days ago
End-to-end congestion control for TCP-friendly flows with variable packet size
Current TCP-friendly congestion control mechanisms adjust the packet rate in order to adapt to network conditions and obtain a throughput not exceeding that of a TCP connection op...
Jörg Widmer, Catherine Boutremans, Jean-Yves ...
111
Voted
ADBIS
2009
Springer
127views Database» more  ADBIS 2009»
15 years 7 months ago
Window Update Patterns in Stream Operators
Continuous queries applied over nonterminating data streams usually specify windows in order to obtain an evolving –yet restricted– set of tuples and thus provide timely result...
Kostas Patroumpas, Timos K. Sellis
118
Voted
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
15 years 6 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
118
Voted
DFT
2005
IEEE
178views VLSI» more  DFT 2005»
15 years 6 months ago
Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems
Defect and fault tolerance is being studied in a 3D Heterogeneous Sensor using a stacked chip with sensors located on the top plane, and inter-plane vias connecting these to other...
Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali