555 search results - page 28 / 111 » Iris Recognition Algorithm Optimized for Hardware Implementa... |
129
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EUROPAR
2008
Springer
15 years 4 months ago
2008
Springer
Abstract. Understanding program behavior is at the foundation of program optimization. Techniques for automatic recognition of program constructs characterize the behavior of code ...
101
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DSD
2008
IEEE
15 years 9 months ago
2008
IEEE
Systems on chip (SoC) have much in common with traditional (networked) distributed systems in that they consist of largely independent components with dedicated communication inte...
116
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ASAP
2006
IEEE
15 years 9 months ago
2006
IEEE
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
126
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ICMCS
2009
IEEE
15 years 22 days ago
2009
IEEE
Parallel scalability allows an application to efficiently utilize an increasing number of processing elements. In this paper we explore a design space for parallel scalability for...
116
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ICCAD
2001
IEEE
15 years 12 months ago
2001
IEEE
1 We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique ar...