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DATE
2009
IEEE
137views Hardware» more  DATE 2009»
15 years 9 months ago
aEqualized: A novel routing algorithm for the Spidergon Network On Chip
—We present the aEqualized routing algorithm: a novel algorithm for the Spidergon Network on Chip. AEqualized combines the well known aFirst and aLast algorithms proposed in lite...
Nicola Concer, Salvatore Iamundo, Luciano Bononi
ICCAD
1997
IEEE
75views Hardware» more  ICCAD 1997»
15 years 7 months ago
An exact gate decomposition algorithm for low-power technology mapping
With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. In...
Hai Zhou, D. F. Wong
DATE
1999
IEEE
123views Hardware» more  DATE 1999»
15 years 7 months ago
An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length
Different logic synthesis tasks have been formulated as input encoding problems but restricted to use a minimum number of binary variables. This paper presents an original column ...
Manuel Martínez, Maria J. Avedillo, Jos&eac...
ICASSP
2011
IEEE
14 years 6 months ago
OpenBliSSART: Design and evaluation of a research toolkit for Blind Source Separation in Audio Recognition Tasks
We describe and evaluate our toolkit openBliSSART (open-source Blind Source Separation for Audio Recognition Tasks), which is the C++ framework and toolbox that we have successful...
Felix Weninger, Alexander Lehmann, Björn Schu...
ATS
2003
IEEE
93views Hardware» more  ATS 2003»
15 years 8 months ago
Optimal System-on-Chip Test Scheduling
1 In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an exi...
Erik Larsson, Hideo Fujiwara