555 search results - page 30 / 111 » Iris Recognition Algorithm Optimized for Hardware Implementa... |
131
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CSE
2009
IEEE
15 years 9 months ago
2009
IEEE
—Interaction with mobile devices that are intended for everyday use is challenging since such systems are continuously optimized towards small outlines. Watches are a particularl...
105
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ISQED
2002
IEEE
15 years 8 months ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
137
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ISSS
1997
IEEE
15 years 7 months ago
1997
IEEE
- An approach for broadband modem FIR filter design optimization is presented. It addresses the minimization of the number of addersubtractors used in the hardware implementation o...
138
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DSD
2004
IEEE
15 years 6 months ago
2004
IEEE
In this paper we present an analysis of the minimal hardware precision required to implement Support Vector Machine (SVM) classification within a Logarithmic Number System archite...
133
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RTCSA
2005
IEEE
15 years 8 months ago
2005
IEEE
We present an approach to the analysis and optimization of heterogeneous distributed embedded systems for hard real-time applications. The systems are heterogeneous not only in te...