555 search results - page 37 / 111 » Iris Recognition Algorithm Optimized for Hardware Implementa... |
151
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ISSS
1995
IEEE
15 years 6 months ago
1995
IEEE
This paper presents a system level design methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. These heterogeneous systems,...
176
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FCCM
2008
IEEE
15 years 9 months ago
2008
IEEE
With a multitude of technological innovations, one emerging trend in image processing, and medical image processing, in particular, is custom hardware implementation of computatio...
ASPDAC
2005
ACM
15 years 5 months ago
2005
ACM
— In this paper we present a scheme for reducing the amount of synchronization overhead needed between components, after HW/SW partitioning, to preserve the original control flo...
129
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ICCAD
2009
IEEE
15 years 24 days ago
2009
IEEE
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...
126
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ASPDAC
2000
ACM
15 years 7 months ago
2000
ACM
- This paper introduces the first hardwarekoftware co-synthesis algorithm that optimizes the implementations of ASICs that are used as processing elements for the embedded systems....