555 search results - page 45 / 111 » Iris Recognition Algorithm Optimized for Hardware Implementa... |
142
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DATE
2005
IEEE
15 years 8 months ago
2005
IEEE
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
ISCAS
2006
IEEE
15 years 9 months ago
2006
IEEE
—This paper presents a Frequency-Estimation Algorithm for the ADPLL designs instead of traditional binary frequency-search algorithm. With the proposed ADPLL architecture and syn...
133
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ICCAD
2001
IEEE
15 years 12 months ago
2001
IEEE
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling a...
107
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DATE
2000
IEEE
15 years 7 months ago
2000
IEEE
This paper presents a single chip implementation of a space-time algorithm for co-channel interference (CCI) and intersymbol interference (ISI) reduction in GSM/DCS systems. The t...
129
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IROS
2009
IEEE
15 years 9 months ago
2009
IEEE
— In this paper, we introduce a high-speed vision platform, H3 (Hiroshima Hyper Human) Vision, which can simultaneously process a 1024× 1024 pixel image at 1000 fps and a 256× ...