555 search results - page 48 / 111 » Iris Recognition Algorithm Optimized for Hardware Implementa... |
122
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ASPDAC
2007
ACM
15 years 7 months ago
2007
ACM
Abstract: This paper presents an approach to area optimization of arithmetic datapaths that perform polynomial computations over bit-vectors with finite widths. Examples of such de...
115
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ICCD
2004
IEEE
16 years 1 days ago
2004
IEEE
This paper proposes a new formalism for layout-driven optimization of datapaths. It is based on preserving an arithmetic bit level representation of the arithmetic circuit portion...
104
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DATE
2006
IEEE
15 years 9 months ago
2006
IEEE
Conventional high-level synthesis uses the worst case delay to relate all inputs to all outputs of an operation. This is a very conservative approximation of reality, especially i...
114
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ASPDAC
2008
ACM
15 years 5 months ago
2008
ACM
In this paper we present a mathematical programming formulation of the integer time budgeting problem for directed acyclic graphs. In particular, we formally prove that our constr...
128
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FCCM
2009
IEEE
15 years 10 months ago
2009
IEEE
Abstract—Precision analysis and optimization is very important when transforming a floating-point algorithm into fixedpoint hardware implementations. The core analysis techniqu...