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SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
15 years 9 months ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
DATE
2003
IEEE
115views Hardware» more  DATE 2003»
15 years 8 months ago
Control Flow Driven Splitting of Loop Nests at the Source Code Level
This paper presents a novel source code transformation for control flow optimizationcalled loop nest splitting which minimizes the number of executed if-statements in loop nests ...
Heiko Falk, Peter Marwedel
ASAP
2007
IEEE
97views Hardware» more  ASAP 2007»
15 years 5 months ago
FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers
This paper presents an optimized design approach of two’s complement large-size squarers using embedded multipliers in FPGAs. The realization is based on BaughWooley’s algorit...
Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, ...
DATE
2006
IEEE
119views Hardware» more  DATE 2006»
15 years 6 months ago
Compiler-driven FPGA-area allocation for reconfigurable computing
In this paper, we propose two FPGA-area allocation algorithms based on profiling results for reducing the impact on performance of dynamic reconfiguration overheads. The problem o...
Elena Moscu Panainte, Koen Bertels, Stamatis Vassi...
SCP
1998
107views more  SCP 1998»
15 years 2 months ago
A Distributed Arc-Consistency Algorithm
Consistency techniques are an e cient way of tackling constraint satisfaction problems (CSP). In particular, various arc-consistency algorithms have been designed such as the time...
T. Nguyen, Yves Deville