Sciweavers

555 search results - page 58 / 111
» Iris Recognition Algorithm Optimized for Hardware Implementa...
Sort
View
ISQED
2006
IEEE
94views Hardware» more  ISQED 2006»
15 years 9 months ago
System-Level SRAM Yield Enhancement
It is well known that SRAM constitutes a large portion of modern integrated circuits, with 80% or more of the total transistors being dedicated to SRAM in a typical processor or S...
Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park...
CGF
2004
151views more  CGF 2004»
15 years 3 months ago
Deferred Splatting
In recent years it has been shown that, above a certain complexity, points become the most efficient rendering primitives. Although the programmability of the lastest graphics har...
Gaël Guennebaud, Loïc Barthe, Mathias Pa...
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
15 years 8 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
CAV
2001
Springer
107views Hardware» more  CAV 2001»
15 years 7 months ago
Job-Shop Scheduling Using Timed Automata
In this paper we show how the classical job-shop scheduling problem can be modeled as a special class of acyclic timed automata. Finding an optimal schedule corresponds, then, to n...
Yasmina Abdeddaïm, Oded Maler
ATS
2001
IEEE
137views Hardware» more  ATS 2001»
15 years 6 months ago
Compaction Schemes with Minimum Test Application Time
Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os...
Ozgur Sinanoglu, Alex Orailoglu