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GECCO
2007
Springer
138views Optimization» more  GECCO 2007»
15 years 9 months ago
Reducing the number of transistors in digital circuits using gate-level evolutionary design
This paper shows that the evolutionary design of digital circuits which is conducted at the gate level is able to produce human-competitive circuits at the transistor level. In ad...
Zbysek Gajda, Lukás Sekanina
ASAP
2005
IEEE
142views Hardware» more  ASAP 2005»
15 years 8 months ago
Decimal Floating-Point Square Root Using Newton-Raphson Iteration
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
Liang-Kai Wang, Michael J. Schulte
DATE
2010
IEEE
154views Hardware» more  DATE 2010»
15 years 8 months ago
ERSA: Error Resilient System Architecture for probabilistic applications
There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware. Traditional redundancy techniques are expensive for...
Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. J...
DATE
2009
IEEE
138views Hardware» more  DATE 2009»
15 years 7 months ago
An approximation scheme for energy-efficient scheduling of real-time tasks in heterogeneous multiprocessor systems
As application complexity increases, modern embedded systems have adopted heterogeneous processing elements to enhance the computing capability or to reduce the power consumption. ...
Chuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo, Lothar...
ICRA
2005
IEEE
124views Robotics» more  ICRA 2005»
15 years 8 months ago
Physical Path Planning Using the GNATs
— We continue our investigation into the application of pervasive, embedded networks to support multi-robot tasks. In this work we use a new a hardware platform, the GNATs, to ai...
Keith J. O'Hara, Victor Bigio, Eric R. Dodson, Ary...