555 search results - page 73 / 111 » Iris Recognition Algorithm Optimized for Hardware Implementa... |
106
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MICRO
2006
IEEE
15 years 9 months ago
2006
IEEE
VLIW and EDGE (Explicit Data Graph Execution) architectures rely on compilers to form high-quality hyperblocks for good performance. These compilers typically perform hyperblock f...
107
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SC
2004
ACM
15 years 8 months ago
2004
ACM
The Merrimac supercomputer uses stream processors and a highradix network to achieve high performance at low cost and low power. The stream architecture matches the capabilities o...
146
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VMV
2003
15 years 4 months ago
2003
This paper presents a method to capture human motion from silhouettes of a person in multi-view video streams. Applying a hierarchical kinematic body model motion parameters are e...
104
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ASPDAC
2005
ACM
15 years 5 months ago
2005
ACM
Abstract— As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted on interconnects of even moderate length for both critical paths and fixing...
129
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ICCAD
2004
IEEE
15 years 12 months ago
2004
IEEE
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...