555 search results - page 75 / 111 » Iris Recognition Algorithm Optimized for Hardware Implementa... |
107
click to vote
ISCAS
2007
IEEE
15 years 9 months ago
2007
IEEE
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...
106
click to vote
DAC
2002
ACM
16 years 4 months ago
2002
ACM
In this paper, we present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Most ...
117
click to vote
ICCAD
1995
IEEE
15 years 6 months ago
1995
IEEE
—A problem in technology mapping is that the quality of the final implementation depends significantly on the initially provided circuit structure. This problem is critical, es...
116
click to vote
TVLSI
2008
15 years 2 months ago
2008
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
114
Voted
ISSS
2002
IEEE
15 years 8 months ago
2002
IEEE
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...