555 search results - page 81 / 111 » Iris Recognition Algorithm Optimized for Hardware Implementa... |
150
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ICCAD
2007
IEEE
15 years 6 months ago
2007
IEEE
Stepwise refinement is at the core of many approaches to synthesis and optimization of hardware and software systems. For instance, it can be used to build a synthesis approach for...
136
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CAV
1997
Springer
15 years 6 months ago
1997
Springer
We demonstrate the feasibility of using the XSB tabled logic programming system as a programmable fixed-point engine for implementing efficient local model checkers. In particular,...
136
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ICCAD
2007
IEEE
15 years 12 months ago
2007
IEEE
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
204
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OSN
2011
14 years 5 months ago
2011
—This paper presents PI-OPS (Parallel-Iterative Optical Packet Scheduler) a parallel-iterative scheduler for asynchronous Optical Packet Switching nodes with optical buffering. O...
126
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SIGIR
2005
ACM
15 years 8 months ago
2005
ACM
We introduce a new model for semantic annotation and retrieval from image databases. The new model is based on a probabilistic formulation that poses annotation and retrieval as c...