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123
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SIPS
2006
IEEE
15 years 9 months ago
Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
Ning Chen, Yongmei Dai, Zhiyuan Yan
120
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ISCAS
2005
IEEE
147views Hardware» more  ISCAS 2005»
15 years 8 months ago
A heuristic approach for multiple restricted multiplication
— This paper introduces a heuristic solution to the multiple restricted multiplication (MRM) optimization problem. MRM refers to a situation where a single variable is multiplied...
Nalin Sidahao, George A. Constantinides, Peter Y. ...
VTS
2005
IEEE
89views Hardware» more  VTS 2005»
15 years 8 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
108
Voted
ISCAS
2003
IEEE
172views Hardware» more  ISCAS 2003»
15 years 8 months ago
Efficient symbol synchronization techniques using variable FIR or IIR interpolation filters
Maximum Likelihood estimation theory can be used to develop optimal timing recovery schemes for digital communication systems. Tunable digital interpolation filters are commonly ...
Martin Makundi, Timo I. Laakso
JMM2
2006
219views more  JMM2 2006»
15 years 2 months ago
Fully Automatic Real-Time 3D Object Tracking using Active Contour and Appearance Models
This paper presents an efficient, robust and fully automatic real-time system for 3D object pose tracking in image sequences. The developed application integrates two main componen...
Giorgio Panin, Alois Knoll