485 search results - page 74 / 97 » Iterative Bounding LAO |
ICCAD
2006
IEEE
15 years 7 months ago
2006
IEEE
Stalls, due to mis-matches in communication rates, are a major performance obstacle in pipelined circuits. If the rate of data production is faster than the rate of consumption, t...
67
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ICCAD
2005
IEEE
15 years 7 months ago
2005
IEEE
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
CVPR
2010
IEEE
15 years 6 months ago
2010
IEEE
Many computer vision problems involving feature correspondence among images can be formulated as an assignment problem with a quadratic cost function. Such problems are computatio...
CVPR
2010
IEEE
15 years 6 months ago
2010
IEEE
Recent advances in scene understanding and related tasks
have highlighted the importance of using regions to reason
about high-level scene structure. Typically, the regions are
...
106
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DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...