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138
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ICSE
2001
IEEE-ACM
15 years 9 months ago
Fast Formal Analysis of Requirements via "Topoi Diagrams"
Early testing of requirements can decrease the cost of removing errors in software projects. However, unless done carefully, that testing process can significantly add to the cos...
Tim Menzies, John D. Powell, Michael E. Houle
138
Voted
ATS
2000
IEEE
134views Hardware» more  ATS 2000»
15 years 9 months ago
Fsimac: a fault simulator for asynchronous sequential circuits
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, ...
DATE
2000
IEEE
114views Hardware» more  DATE 2000»
15 years 9 months ago
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths
Designs which do not fully utilize their arithmetic datapath components typically exhibit a significant overhead in power consumption. Whenever a module performs an operation who...
Michael Münch, Norbert Wehn, Bernd Wurth, Ren...
133
Voted
ICC
2000
IEEE
15 years 9 months ago
A Framework for the Analysis of Adaptive Voice over IP
— In this paper, we present a framework for the analysis of a set of adaptive variable-bit-rate voice sources in a packet network. The instantaneous bit rate of each source is de...
Claudio Casetti, J. C. De Martin, Michela Meo
145
Voted
ICCD
2000
IEEE
120views Hardware» more  ICCD 2000»
15 years 9 months ago
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
This paper presents a verification technique for functional comparison of large combinational circuits using a novel combination of known approaches. The idea is based on a tight...
Viresh Paruthi, Andreas Kuehlmann
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