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CODES
2004
IEEE
15 years 7 months ago
Optimizing the memory bandwidth with loop fusion
The memory bandwidth largely determines the performance and energy cost of embedded systems. At the compiler level, several techniques improve the memory bandwidth at the scope of...
Paul Marchal, José Ignacio Gómez, Fr...
CODES
2004
IEEE
15 years 7 months ago
A novel deadlock avoidance algorithm and its hardware implementation
This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provi...
Jaehwan Lee, Vincent John Mooney III
144
Voted
CASES
2006
ACM
15 years 7 months ago
Power efficient branch prediction through early identification of branch addresses
Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the embedded processor domain, requiring the incorporation of dynamic b...
Chengmo Yang, Alex Orailoglu
133
Voted
DATE
2004
IEEE
151views Hardware» more  DATE 2004»
15 years 7 months ago
Dynamic Voltage and Cache Reconfiguration for Low Power
Given a set of real-time tasks scheduled using the earliest deadline first (EDF) algorithm, we discuss two techniques for reducing power consumption while meeting all timing requi...
André C. Nácul, Tony Givargis
CCGRID
2006
IEEE
15 years 7 months ago
Mirroring Resources or Mapping Requests: Implementing WS-RF for Grid Workflows
The Web Services Resource Framework (WS-RF) and the Web Services Notification (WS-N) specifications are a crucial component of Grid infrastructures. They provide a standardized int...
Thomas Heinis, Cesare Pautasso, Gustavo Alonso
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