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128
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DSN
2004
IEEE
15 years 7 months ago
An Architectural Framework for Providing Reliability and Security Support
This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level framework called the Reliability and Security Engine (RSE)...
Nithin Nakka, Zbigniew Kalbarczyk, Ravishankar K. ...
CHES
2006
Springer
158views Cryptology» more  CHES 2006»
15 years 7 months ago
Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller
8-bit microcontrollers like the 8051 still hold a considerable share of the embedded systems market and dominate in the smart card industry. The performance of 8-bit microcontrolle...
Manuel Koschuch, Joachim Lechner, Andreas Weitzer,...
135
Voted
CODES
2006
IEEE
15 years 7 months ago
Increasing hardware efficiency with multifunction loop accelerators
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
132
Voted
GECCO
2006
Springer
155views Optimization» more  GECCO 2006»
15 years 7 months ago
Comparison of genetic representation schemes for scheduling soft real-time parallel applications
This paper presents a hybrid technique that combines List Scheduling (LS) with Genetic Algorithms (GA) for constructing non-preemptive schedules for soft real-time parallel applic...
Yoginder S. Dandass, Amit C. Bugde
CASES
2001
ACM
15 years 7 months ago
Heads and tails: a variable-length instruction format supporting parallel fetch and decode
Abstract. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and de...
Heidi Pan, Krste Asanovic
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