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ANCS
2007
ACM
15 years 6 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
15 years 6 months ago
Software Performance Estimation in MPSoC Design
- Estimation tools are a key component of system-level methodologies, enabling a fast design space exploration. Estimation of software performance is essential in current software-...
Márcio Oyamada, Flávio Rech Wagner, ...
GLVLSI
2009
IEEE
170views VLSI» more  GLVLSI 2009»
15 years 6 months ago
Physical unclonable function and true random number generator: a compact and scalable implementation
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...
Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, P...
COMPSAC
2004
IEEE
15 years 5 months ago
Towards Autonomic Computing Middleware via Reflection
ion Abstracts Zizhan Zheng, Qianxiang Wang, Gang Huang and Hong Mei. Design and Implementation of the Load Balancing Mechanism in PKUAS (in Chinese). ACTA ELECTRONICA SINICA, 32(12...
Gang Huang, Tiancheng Liu, Hong Mei, Zizhan Zheng,...
FPL
2004
Springer
144views Hardware» more  FPL 2004»
15 years 5 months ago
A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms
A recent trend towards integrating FPGAs with many heterogeneous components, such as memory systems, dedicated multipliers, etc., has made them an attractive option for implementin...
Jingzhao Ou, Viktor K. Prasanna
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