In this paper we present a genetic approach for the efficient generation of an encoder to minimize switching activity on the high-capacity lines of a communication bus. The appro...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
This presentation demonstrates the early results from the French ANR project RT-Simex. RT-Simex proposes a set of tools to analyze timing of parallel embedded code and trace the s...
Abstract. A removable visible watermarking scheme, which operates in the discrete cosine transform (DCT) domain, is proposed for combating copyright piracy. First, the original wat...
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
Abstract. Memory access latency can limit microcontroller system performance. SDRAM access control policies impact latency through SDRAM device state. It is shown that execution ti...