With their increasingly powerful computational resources and high-speed wireless communications, future mobile systems will have the ability to run sophisticated applications on c...
In this paper, we describe the design and evaluation of a scheduler (referred to as Everest) for allocating processors to services in high performance, multi-service routers. A sc...
Ravi Kokku, Upendra Shevade, Nishit Shah, Ajay Mah...
—The convergence of application domains in new systems-on-chip (SoC) results in systems with many applications with a mix of soft and hard real-time requirements. To reduce cost,...
In archiectural synthesis, scheduling and resource allocation are important steps. During the early stage of the design, imprecise information is unavoidable. Under the imprecise ...
In deep submicron technology, wire delay is no longer negligible and is gradually dominating the system latency. Some state-of-the-art architectural synthesis flows adopt the distr...