Sciweavers

45 search results - page 7 / 9
» KCube: A novel architecture for interconnection networks
Sort
View
IPPS
1999
IEEE
15 years 1 months ago
NetCache: A Network/Cache Hybrid for Multiprocessors
In this paper we propose the use of an optical network not only as the communication medium, but also as a system-wide cache for the shared data in a multiprocessor. More specifica...
Enrique V. Carrera, Ricardo Bianchini
CODES
2008
IEEE
14 years 11 months ago
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip
The performance of system-on-chip is determined not only by the performance of its functional units, but also by how efficiently they cooperate with one another. It is the on-chip...
Huaxi Gu, Jiang Xu, Zheng Wang
TMM
2002
81views more  TMM 2002»
14 years 9 months ago
Staggered push - a linearly scalable architecture for push-based parallel video servers
With the rapid performance improvements in low-cost PCs, it becomes increasingly practical and cost-effective to implement large-scale video-on-demand (VoD) systems around parallel...
Jack Y. B. Lee
MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
15 years 4 months ago
A case for dynamic frequency tuning in on-chip networks
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
Asit K. Mishra, Reetuparna Das, Soumya Eachempati,...
87
Voted
VLSID
2002
IEEE
138views VLSI» more  VLSID 2002»
15 years 10 months ago
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
Haris Lekatsas, Jörg Henkel