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CGO
2004
IEEE
15 years 1 months ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
DATE
2004
IEEE
144views Hardware» more  DATE 2004»
15 years 1 months ago
A Framework for Battery-Aware Sensor Management
A distributed sensor network (DSN) designed to cover a given region R, is said to be alive if there is at least one subset of sensors that can collectively cover (sense) the regio...
Sridhar Dasika, Sarma B. K. Vrudhula, Kaviraj Chop...
DCC
2004
IEEE
15 years 1 months ago
Adaptive Rate Control Scheme for Video Streaming Over Wireless Channels
Providing continuous video playback with graceful quality degradation over wireless channels is fraught with challenges. Video applications require stringent delay guarantees and ...
Marwan Krunz, Mohamed Hassan
CF
2006
ACM
15 years 1 months ago
The potential of the cell processor for scientific computing
The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As...
Samuel Williams, John Shalf, Leonid Oliker, Shoaib...
EDOC
2004
IEEE
15 years 1 months ago
Evaluating the Performance of Middleware Load Balancing Strategies
This paper presents three contributions to research on middleware load balancing. First, it describes the design of Cygnus, which is an extensible open-source middleware framework...
Jaiganesh Balasubramanian, Douglas C. Schmidt, Law...