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ISPD
2010
ACM
217views Hardware» more  ISPD 2010»
15 years 4 months ago
ITOP: integrating timing optimization within placement
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy,...
IPSN
2010
Springer
15 years 4 months ago
KleeNet: discovering insidious interaction bugs in wireless sensor networks before deployment
Complex interactions and the distributed nature of wireless sensor networks make automated testing and debugging before deployment a necessity. A main challenge is to detect bugs ...
Raimondas Sasnauskas, Olaf Landsiedel, Muhammad Ha...
ACSAC
2009
IEEE
15 years 4 months ago
MAVMM: Lightweight and Purpose Built VMM for Malware Analysis
—Malicious software is rampant on the Internet and costs billions of dollars each year. Safe and thorough analysis of malware is key to protecting vulnerable systems and cleaning...
Anh M. Nguyen, Nabil Schear, HeeDong Jung, Apeksha...
AOSD
2009
ACM
15 years 4 months ago
Modelling hardware verification concerns specified in the e language: an experience report
e is an aspect-oriented hardware verification language that is widely used to verify the design of electronic circuits through the development and execution of testbenches. In rec...
Darren Galpin, Cormac Driver, Siobhán Clark...
DAC
2009
ACM
15 years 4 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
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