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IEEEPACT
2007
IEEE
15 years 8 months ago
Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking
Under current worst-case design practices, manufacturers specify conservative values for processor frequencies in order to guarantee correctness. To recover some of the lost perfo...
Brian Greskamp, Josep Torrellas
SBCCI
2005
ACM
185views VLSI» more  SBCCI 2005»
15 years 7 months ago
Automatic generation of test sets for SBST of microprocessor IP cores
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
Ernesto Sánchez, Matteo Sonza Reorda, Giova...
JOI
2008
51views more  JOI 2008»
15 years 1 months ago
International collaboration in science and the formation of a core group
International collaboration as measured by co-authorship relations on refereed papers grew linearly from 1990 to 2005 in terms of the number of papers, but exponentially in terms ...
Loet Leydesdorff, Caroline S. Wagner
ICCD
2006
IEEE
185views Hardware» more  ICCD 2006»
15 years 11 months ago
An accurate Energy estimation framework for VLIW Processor Cores
— In this paper, we present a comprehensive energy estimation framework for software executing on Very Long Instruction Word (VLIW) processor cores. The proposed energy model is ...
Sourav Roy, Rajat Bhatia, Ashish Mathur
HPDC
2008
IEEE
15 years 8 months ago
Harmony: an execution model and runtime for heterogeneous many core systems
The emergence of heterogeneous many core architectures presents a unique opportunity for delivering order of magnitude performance increases to high performance applications by ma...
Gregory F. Diamos, Sudhakar Yalamanchili