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ANCS
2007
ACM
15 years 3 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos
WOTUG
2008
15 years 1 months ago
Representation and Implementation of CSP and VCR Traces
Abstract. Communicating Sequential Processes (CSP) was developed around a formal algebra of processes and a semantics based on traces (and failures and divergences). A trace is a r...
Neil C. C. Brown, Marc L. Smith
114
Voted
IJDE
2007
123views more  IJDE 2007»
14 years 11 months ago
Identifying Authorship by Byte-Level N-Grams: The Source Code Author Profile (SCAP) Method
Source code author identification deals with identifying the most likely author of a computer program, given a set of predefined author candidates. There are several scenarios whe...
Georgia Frantzeskou, Efstathios Stamatatos, Stefan...
91
Voted
DAC
2001
ACM
16 years 19 days ago
Hardware/Software Instruction Set Configurability for System-on-Chip Processors
New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned lo...
Albert Wang, Earl Killian, Dror E. Maydan, Chris R...
HPCA
2001
IEEE
16 years 1 days ago
An Architectural Evaluation of Java TPC-W
The use of the Java programming language for implementing server-side application logic is increasing in popularity, yet there is very little known about the architectural require...
Harold W. Cain, Ravi Rajwar, Morris Marden, Mikko ...