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» Language Modeling and Encryption on Packet Switched Networks
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ERSA
2010
172views Hardware» more  ERSA 2010»
14 years 9 months ago
A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
Heiner Giefers, Marco Platzner
HYBRID
2001
Springer
15 years 4 months ago
Hybrid Modeling and Simulation of Biomolecular Networks
Abstract. In a biological cell, cellular functions and the genetic regulatory apparatus are implemented and controlled by a network of chemical reactions in which regulatory protei...
Rajeev Alur, Calin Belta, Franjo Ivancic
ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
15 years 5 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic
INFOCOM
2003
IEEE
15 years 5 months ago
The effect of layer-2 store-and-forward devices on per-hop capacity estimation
— Tools such as pathchar, clink, and pchar attempt to measure the capacity of every Layer-3 (L3) hop in a network path. These tools use the same underlying measurement methodolog...
Ravi Prasad, Constantinos Dovrolis, Bruce A. Mah
103
Voted
TACS
2001
Springer
15 years 4 months ago
The UDP Calculus: Rigorous Semantics for Real Networking
Network programming is notoriously hard to understand: one has to deal with a variety of protocols (IP, ICMP, UDP, TCP etc), concurrency, packet loss, host failure, timeouts, the c...
Andrei Serjantov, Peter Sewell, Keith Wansbrough