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176
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RTAS
1997
IEEE
15 years 7 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
141
Voted
PVM
1997
Springer
15 years 7 months ago
Message-Passing Program Development by Ensemble
We present Ensemble, a message-passing implementation methodology, applied to PVM. Ensemble overcomes problems and complexities in developing applications in messagepassing enviro...
John Yiannis Cotronis
135
Voted
EUROCAST
2007
Springer
122views Hardware» more  EUROCAST 2007»
15 years 7 months ago
Generation of Indexes for Compiling Efficient Parsers from Formal Specifications
abstract Parsing schemata [4] provide a formal, simple and uniform way to describe, analyze and compare different parsing algorithms. The notion of a parsing schema comes from cons...
Carlos Gómez-Rodríguez, Miguel A. Al...
155
Voted
MSO
2003
15 years 4 months ago
Simulation based Development of Efficient Hardware for Sort based Algorithms
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...
Niklas Hansson, Jay H. Harris
132
Voted
COLING
1992
15 years 4 months ago
The Proper Treatment Of Word Order In HPSG
: This paper describes a possibility of expressing ordering constraints among non-sister constituents in binary branching syntactic structures on a local basis, supported by viewin...
Karel Oliva