751 search results - page 28 / 151 » Large Event Traces in Parallel Performance Analysis |
ICPP
1999
IEEE
15 years 5 months ago
1999
IEEE
Trace-level reuse is based on the observation that some traces (dynamic sequences of instructions) are frequently repeated during the execution of a program, and in many cases, th...
124
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ICCAD
1999
IEEE
15 years 5 months ago
1999
IEEE
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. ...
117
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IJHPCA
2010
14 years 10 months ago
2010
Emergence of new parallel architectures presents new challenges for application developers. Supercomputers vary in processor speed, network topology, interconnect communication ch...
ICPP
2009
IEEE
15 years 8 months ago
2009
IEEE
Abstract—The Charm++ parallel programming system provides a modular performance interface that can be used to extend its performance measurement and analysis capabilities. The in...
104
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IPPS
2009
IEEE
15 years 8 months ago
2009
IEEE
Grid jobs often consist of a large number of tasks. If the performance of a statically scheduled grid job is unsatisfactory, one must decide which code of which task should be imp...